IP Release Principal Engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

The IP Release Principal Engineer is a senior technical individual contributor within Marvell's IP Subsystem (IPSS) Center of Excellence (COE). This role is the quality gatekeeper and first line of technical support for all IP subsystem deliveries - ensuring that every IP package released to SoC integrators and external customers meets Marvell's stringent quality, completeness, and methodology standards.

The engineer will own and drive the complete front-end release qualification flow - from RTL static checks through synthesis readiness and DFT enablement - and will serve as the primary point of contact for IP delivery questions, issues, and triage across COE teams and consuming SoC programs.

Key Responsibilities
Static Analysis & RTL Quality

• Own the full RTL static analysis sign-off flow including Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks using Industry standard tools.

• Review and approve RTL static waivers; ensure all waivers are justified, documented, and included in the IP release package.

Synthesis

• Drive front-end synthesis readiness for each IP subsystem using multiple EDA tools; validate synthesis scripts, timing constraints (SDC), and UPF.

• Work with IPSS COE Implementation Engineers to alidate that IP releases meet synthesis quality bars: clean Analyze/Elaborate, no unconstrained endpoints, and representative PPA metrics (area, timing, power).

DFT (Design for Test)

• Ensure early DFT consideration is built into each IP subsystem - including scan insertion readiness, BIST hooks, JTAG, and boundary scan.

• Review RTL DFT handoff collateral (filelists, SDC, CDC constraints for DFT), and validate that IP packages are DFT-ready for downstream insertion flows.

• Serve as COE liaison to DFT teams; triage DFT-related blockers for IP releases and drive resolution across design and DFT engineering teams.

IP Delivery Checklist & Release Qualification

• Own and execute the IP delivery checklist at each milestone (iRTL, Code Complete, RTLF), verifying completeness of all required collateral including: RTL source files, file manifests (.f/.vc), SDC, UPF, memory lists, CDC crossing lists, static waivers, CSR/register descriptions, synthesis scripts, and integration guidelines.

• Ensure alignment of IP releases with requirements and delivery standards.

• Validate IP release packaging through IPMP and ensure versioned, traceable releases are distributed to SoC teams and external customers.

• Maintain and publish IP release quality dashboards and metrics (delivery status, checklist completion, open issues).

First Line of Support for IP Delivery

• Act as the primary technical point of contact for SoC integration teams consuming COE IP subsystems - triaging and resolving IP integration issues related to static checks, synthesis, and DFT.

• Manage IP delivery escalations; track bugs and action items in Jira; provide timely updates to consuming program teams.

• Provide integration guidance (RTL guidelines, constraints usage, CDC/RDC methodology, synthesis configuration) to SoC engineers adopting COE IP subsystems.

• Interface with third-party IP vendors to review quality metrics (Lint/CDC/RDC results, synthesis reports, DFT support) as part of IP onboarding and evaluation.

Cross-Functional Collaboration

• Collaborate closely with TFM team, Central Engineering, SoC teams, DFT, PD, FW/SW, and emulation teams to ensure IP packages meet all downstream requirements.

• Participate in methodology working groups to align on Lint/CDC/RDC rule sets, tool selection, and checkpoint requirements.

• Contribute to AI automation to reduce manual effort and increase consistency of IP release flows.

What We're Looking For

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience or equivalent professional experience in lieu of a formal degree

• Domain Expertise of SoC architecture, processor cores, memory, PCIE/CXL highly preferred

• Ethernet, Security and peripheral interfaces through hands on prior experience preferred

• Experience with Large and complex design synthesis, Floor planning, Place and Route, Clock tree and Timing closure of large Subsystems

• Extensive experience in Verilog and Static Quality checks of the implemented RTL

• Experience with Memory generation highly preferred

• Experience with leading foundries and latest process nodes 2nm, 3nm, 5nm etc preferred

• Hands on experience in interpretive language such as Perl/Python

• Proven track record of delivering production-quality designs on aggressive development schedules

• Good communication skills and self-discipline contributing in a team environment

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.