New 
Senior Signal and Power Integrity Engineer
 Microsoft | |
 United States, North Carolina, Raleigh | |
 Sep 26, 2025 | |
|
OverviewMicrosoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state of the art custom computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. We are seeking a Senior Signal Integrity and Power Integrity (SIPI) Engineer to join the engineering team responsible for developing advanced power delivery and signaling solutions for High Performance Computing (HPC) silicon designs. In this role, you will be responsible for driving the completion of SIPI design solutions supporting overall SOC performance interfacing with silicon, packaging, and system design teams.
ResponsibilitiesThe SMPE silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner. SIPI engineer for compute and AI SoCs and platforms - Implement strategies for end-to-end power delivery design and signal integrity design from Silicon to Package, and linking to Platform to System and CloudDeliver SIPI solutions that meet the HPC demands across the entire system.Drive future power and signal integrity solutions for chiplet architecture with advanced packaging and advanced silicon nodesDesign, model, and simulate SI and PI (i.e., incl. IP design, voltage regulator, motherboard, CPU package, silicon, and decoupling capacitor solution) for data center processors and corresponding platforms to ensure optimized performance. Performs DC, AC and transient simulation to provide noise, impedance profile of the whole power delivery path and link/electrical simulations to validate I/O performance from platform to silicon.Work closely with silicon and platform architects, motherboard and package designers, thermal architects and engineers, and power and performance engineers.Drives the execution of architecture solutions across product lines or multiple product groups across teams that account for design trends and future concepts by leveraging cross- functional expertise, industry best practices, and lessons learned from teams working across multiple product linesDrives engineering system design decisions that require collaboration between internal and external stakeholders to account for platform-specific technology decisions and develop system models based on current and anticipated feature/design needs and trade-offs. | |